• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    System and method of generating images on tft screens comprising flash memories (1.3) with serial interface where some characters to be displayed are stored and a microcontroller (1.2), where the microcontroller (1.2) comprises a timer module (1.22) that generates a signal proportional to a programmable clock signal; a serial peripheral interface port (1.23) to manage flash memories; a general purpose input/output pins (1.24) to enable writing on the tft screen; and where the system is configured to transmit the characters stored in flash memories directly to the tft screen without interposition of ram memories or tft drivers. (Machine-translation by Google Translate, not legally binding)
    公开号:ES2606299A1
    申请号:ES201531213
    申请日:2015-08-21
    公开日:2017-03-23
    发明作者:Jesús Manuel HERNÁNDEZ MANGAS；Jesús ARIAS ÁLVAREZ
    申请人:Universidad de Valladolid；
    IPC主号:
    专利说明:

    DESCRIPTION

    GENERATION SYSTEM AND PROCEDURE
    OF IMAGES ON TFT SCREENS
     5
    OBJECT OF THE INVENTION

    The present invention relates to a novel system and method of generating images on TFT screens (thin film transistor screen) in which predetermined and pre-stored characters or figures are transferred directly from a non-volatile flash memory TFT screen series. Preferably, the invention has been provided for low-cost TFT displays in which the computational capabilities of the electronics associated with the display are limited.
     fifteen
    The solution described here allows the use of general-purpose microcontrollers avoiding the need to integrate specific controllers of TFT displays and internal or external RAM. Additionally, the memory requirements in the general purpose microcontroller are minimal as they are limited to a brief set of pointers instead of the video data themselves relative to the images 20 to be displayed on the TFT screen.

    The invention falls within the technical field of electronic systems for the visualization of content, more specifically in that related to TFT screens.
     25
    BACKGROUND OF THE INVENTION

    Conventional, low-cost conventional electronic displays and display panels are usually based on segmented passive-type LCD (liquid crystal displays) that do not include any integrated electronics and where their terminals connect directly to the LCD electrodes. The electronic control of the LCD screen itself is low cost since the video memory it incorporates is limited to one bit per segment. These types of screens have a series of drawbacks, among which are:
     Poor aesthetics: alphanumeric characters have artificial forms since they break down into a common set of polygonal segments. The separation between the segments is clearly visible.
     Bad contrast: when the number of segments is high (> 40), multiplexing is used through the use of two or more backplanes, which reduces the contrast and may require manual adjustment using potentiometers.
     Monochrome image: contrast problems exclude the possibility of representing images of variable colors. Through techniques such as the sequential field LCD consisting of changing the color of the LCD backlight in a synchronized manner with the refreshment of the segments, 10 simulate up to 16 colors are achieved (US7502004 B2, CN1680994 A, US7557787 B2).

    Another display technology is the TFT screens (US8937691 B2) in which a specific voltage can be applied to each segment (pixel) individually thanks to the switching electronics included in the screen itself based on 15 amorphous silicon MOSFET transistors, that give name to this technology. These types of screens have an image quality far superior to LCD screens. The pixels are smaller than one millimeter in size with three color components, red, green and blue, which can be chosen from a palette of at least 64 levels individually for each pixel, and with resolutions that are around one million pixels, even 20 for small screens. They also have a fairly reduced cost.

    However, these TFT screens require a control electronics (internal or external to the microcontroller) that allows data storage (internal or external RAM) and generates a periodic data refresh to the TFT screen. Documents WO2003021566 A1, CN204178686 U and CN102945658 A describe various TFT controllers. TFT technology implies that even on small screens the volume of data to be transferred is considerable. For example, on a 480x272 pixel screen, 391,680 bytes are needed, which must be transferred to the screen at least every 20 milliseconds to avoid flickering in the image. These 30 amounts of memory far exceed the capacity of the internal memories of current general-purpose microcontrollers, which requires the incorporation of controllers for external dynamic memories in addition to interface peripherals (TFT controllers) for the screen in charge on the TFT screens. of the
    periodic soda of it.

    The image generation systems for conventional TFT screens change the image displayed indirectly: first they write in the area of video RAM destined to refresh the video, and then the TFT controller (peripheral 5 interface) will transfer that data to the display in successive refresh cycles. The graphic character of the images represented translates into a remarkable volume of data that must be modified in the video RAM when large areas of the image are changed, resulting in a slow response to changes. This aspect is not usually relevant in desktop computers because 10 have large bandwidths in their memories and a lot of computing power. But in the microcontrollers that integrate this type of TFT screens for specific applications, such as elevator position indicators, road indicator panels, etc., these resources are usually much more limited. With processors such as the LPC2478, with a clock frequency of less than 15 100MHz, internal RAM and / or Flash memory below the Mbyte and external DRAM of 32 or 16 bits of data width, changes in video memory tend to greatly exceed the duration of a screen refresh cycle, creating a visual sensation of false image persistence.
     twenty
    It should also be noted that in conventional low-cost electronic displays and display panels, the images shown are generally not arbitrary but combinations of predefined figures such as alphanumeric characters of various sizes and fixed icons. These elements have to be stored in the non-volatile memory of the system from which they are transferred to the video RAM when they want to be represented on the screen, so that you have the same information taking up space in two different memories.

    Therefore, the technical problem that arises is the display on TFT screens of predetermined characters or figures by means of a system of generation of 30 images that implies a reduction of components and therefore of economic cost and a reduction of the computing power necessary for do it, with respect to the currently existing solutions

    DESCRIPTION OF THE INVENTION

    In order to solve the problems set forth above, the present invention describes a system and method of generating images on TFT screens in which predetermined figures and previously stored in 5 non-volatile series flash memories are transferred directly to the TFT screen This allows you to use general-purpose microcontrollers without a TFT controller or internal or external RAM.

    Thus, a first object of the present invention is a system of generating 10 images on TFT screens comprising a TFT screen, at least one flash memory with serial interface where characters to be displayed on the TFT screen and a microcontroller are stored. Depending on the type of characters to be displayed or their color needs, a single or several flash memories connected in parallel will be necessary to store the different 15 characters to be displayed. Note that throughout this document when it says "characters" refers to predefined images, letters, numbers, icons or figures, which may have very different sizes and shapes. The capacity of flash memories will determine the shape, size and quantity of characters that are stored. These flash memories with serial interface are external memories to the TFT screen and the microcontroller. The microcontroller comprises:
     - a timer module configured to generate a signal of width proportional to a number of cycles of a clock signal. The number of cycles of the clock signal will be programmable depending on the particularities of the TFT screen and the associated electronics as well as the type of character to be displayed. 25 Each cycle of this signal generated by the timer module corresponds to one pixel of the TFT screen. In addition, the clock signal will be synchronous with the internal clock of the microcontroller. This signal will control the number of clock cycles that are applied to flash memories during data reading;
     - a serial peripheral interface port configured to manage at least 30 flash memory. This port will generate the signals that will enable reading in flash memories;
     - General purpose input / output pins configured to enable writing on the TFT screen. They will also be configured to manage the
    selection of serial flash memories, multiplexing the clock signal of serial flash memories, and selecting the color of the image in embodiments with a color depth of 1 bit per pixel;
     where the system additionally comprises means for generating a clock input signal of the TFT screen from the signal generated by the timer module and the clock signal and a switch that selects a clock signal from the at least a flash memory between the clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, so that the characters in the at least one flash memory are transmitted directly to the TFT screen. 10

    Since general purpose microcontrollers are used (not specifically designed for the management of TFT screens), a specific TFT interface peripheral is also lacking. This implies the need to generate the control signals of both the TFT screen and the flash memories by means of the microcontroller 15 using the usual peripherals integrated therein: synchronous timers and serial ports that help reduce the computational load on the microcontroller's CPU , leaving still an appreciable percentage of the CPU time available to execute the main code of the application.
     twenty
    In a particular embodiment of the invention, the system comprises an internal clock for the generation of the clock signal. This internal clock generally provides a fixed frequency square wave. This signal can also be provided from a clock external to the system.
     25
    In another particular embodiment of the invention, the timer module comprises having an active output selected between an output by comparison and an output with pulse width modulation whereby the signal of width proportional to the clock signal is generated.
     30
    In another particular embodiment of the invention, the at least one single flash memory with serial interface is a peripheral interface memory (SPI) connected in series to the microcontroller.

    In another particular embodiment of the invention, the at least one serial interface flash memory is a quad-serial serial interface (SQI) memory, which is capable of reading 4 bits of data for each clock cycle.

    In another particular embodiment of the invention, the at least one flash memory with 5 serial interface of the system are two quad-serial serial interface (SQI) memories connected in parallel.

    In another particular embodiment of the invention, the system comprises a color allocation module connected to the at least one flash memory to allocate colors to the characters shown on the TFT screen.

    In another particular embodiment of the invention, in the case of having a single peripheral interface memory (SPI) connected in series to the microcontroller, the color allocation module comprises 4 AND doors. Each of the AND doors has a first common input connected to a video output of the serial SPI memory and additionally a second input. Each second input of each AND gate is connected, respectively, to one of the general purpose input / output pins, so that the color assignment module is configured to generate black background monochrome characters. twenty

    In another particular embodiment of the invention, in the case of having a single peripheral interface memory (SPI) connected in series to the microcontroller, the color allocation module comprises a quadruplex multiplexer with an input connected to a video output of the SPI memory, 4 first inputs connected 25 respectively to 4 general purpose input / output pins to assign a color to each character and 4 second inputs respectively connected to 4 general purpose input / output pins to assign a color to a background. In this way, the color assignment module is configured to generate monochrome characters with a monochrome background. 30

    In another particular embodiment of the invention, when a single SQI memory is available, said memory has 4 video outputs directly connected to video inputs of the TFT screen so that the system is configured to
    generate characters with color depths of 4 bits per pixel.

    In another particular embodiment of the invention, when two SQI memories are connected in parallel, each memory has 4 video outputs directly connected to video inputs of the TFT screen, the system 5 being configured to generate characters with color depths 8 bits per pixel.

    Optionally, it is also planned to interconnect more than two SQI memories in parallel to increase the color depth of the generated image, although depths of 8 bits per pixel provide an image quality in photographs 10 more than acceptable (the characters could be Photos).

    A second object of the present invention is a method of generating images on TFT screens that makes use of the system described above. Said procedure comprises the following steps:
     - generate in the timer module a signal of width proportional to a programmable number of cycles of a clock signal;
     - activate a write mode of the TFT screen by means of one of the general purpose output input pins of the microcontroller for a duration of a visible part of a character line; twenty
     - generate a clock input signal from the TFT screen from the signal generated by the timer module and the clock signal;
     -select a signal between a clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, where the selected signal is the clock input signal of the at least 25 flash memory ; Y,
     - send from the at least one flash memory a character from the character line directly to the TFT screen when the switch selects the clock input signal from the TFT screen and the clock input signal from the TFT screen is active. 30

    In a particular embodiment, the method also assigns color to the characters shown on the TFT screen by means of the color assignment module.

    In another particular embodiment, the method sends a number of clock pulses between two active cycles of the TFT display clock input signal to mark a start of a new line of characters.

    In another particular embodiment, when the switch selects the clock signal from the serial peripheral interface port, the method comprises sending read commands to the at least one flash memory.

    Thus, the solution described here has the following advantages over other existing solutions: 10
     - The memory requirements in the microcontroller are minimal as they are limited to a brief set of pointers instead of the video data itself. The change in the value of these pointers will immediately result in the representation of a different image, with no more time elapsing than that of a single refresh cycle; fifteen
     - the existence of a specific TFT screen controller or internal or external RAM memory is not necessary, which simplifies the implementation of the system by reducing the number of components and therefore its economic cost;
     - the transmission of the characters from the flash memories to the TFT screen is done directly from the video output of the memories to the 20 video inputs on the screen (RGB inputs) or through the interposition of very simple logic gates or multiplexers , which significantly reduces the memory needs of the system; Y,
     - duplication of memories is avoided as it is not necessary to include RAM memories. 25

    BRIEF DESCRIPTION OF THE FIGURES

    To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, an integral set of said description is attached, a set of drawings in which, with an illustrative and non-limiting nature, it has been represented the next:

    Figure 1.- Shows the block diagram of an exemplary embodiment of the system of
    Image generation on TFT screens.

    Figure 2.- Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 1 bit per pixel, with 16 possible colors for the foreground and black background. 5

    Figure 3.- Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 1 bit per pixel, 16 possible colors for the foreground and selectable color background among 16 colors. 10

    Figure 4.- Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 4 bits per pixel. The flash memory has a quad-serial serial input / output interface (SQI) with a data width selectable by command of 1 or 4 bits. fifteen

    Figure 5.- Shows the block diagram of an embodiment example of the color assignment module for a depth of 8 bit per pixel. The two flash memories have a quad-serial serial input / output interface (SQI) with a data width selectable by command of 1 or 4 bits. twenty

    Figure 6.- Shows a schedule of an example of the process of generating images on a TFT screen showing the shape of the different control signals generated for the transmission of a video line from the flash memories to the TFT screen. 25

    DESCRIPTION OF VARIOUS EXAMPLES OF EMBODIMENT OF THE INVENTION

    Then, a description of several embodiments of the invention is made, by way of illustration and not limitation, with reference to the numbering adopted in the figures.

    Figure 1 is the block diagram of an embodiment of the image generation system on TFT screens in which the main ones are shown
    components of the aforementioned system and how they connect to each other. These components are: the TFT display (1.1), the general purpose microcontroller (1.2), the integrated peripherals (1.21-1.24) in the microcontroller (1.2), a plurality of serial Flash memories (1.3) with the graphic information (characters ) stored, the clock generation logic (1.4) for the generation of the clock signals of the screen (1.1) and the memories (1.3) and the color generation logic (1.5) that will depend on the depth of desired color In turn, the peripherals integrated in the microcontroller are: a clock generator (1.21), a timer (1.22), a SPI serial port (1.23) and GPIO general purpose input and output pins (1.24).
     10
    More specifically, the system of Figure 1 shows the TFT screen (1.1) with its typical interface signals. TFT displays are synchronous devices, with a clock input (CLK) through which a clock signal (PIXCLK) is received that governs your internal state machine. It is therefore not necessary to follow a rigorous timing during the refresh of the screen, as long as the total count of 15 clock pulses is correct and the total refresh time is not too large and in the place of flickering. In addition, the TFT screens have a data validation (DE) input and two synchronization inputs, horizontal (HSYNC) and vertical (VSYNC), although in many cases these last two signals are optional since they are generated internally from the signal of. These DE, HSYNC and VSYNC inputs are controlled from the GPIO general purpose input and output pins (1.24). The remaining inputs of the TFT screen (1.1) are the video inputs of the screen corresponding to the bits with the level of each color component (R: red, G: green, B: blue) encoded as a binary number of 8 or 6 bits. The bit width will depend on the specific TFT display model (1.1). Said RGB inputs will be connected directly to the specific outputs of the serial flash memories themselves (1.3) or by interposition of logic gates, multiplexers or demultiplexers, among others, that make up the logic of color generation (1.5).

    The other basic component of the system is the microcontroller (1.2), of which only the subsystems involved in the generation of the images towards the TFT screen (1.1) have been represented, but which would have additional subsystems for the management of other related aspects with the control of the TFT screen such as serial communication interfaces (CAN / LIN / RS485 / USB,…) or timers for
    acoustic signal generation, etc. In this particular embodiment, the microcontroller has the following peripherals:
     a clock generator (1.21) that allows a square signal (CLKosc) of a frequency compatible with the display to be obtained on a pin, (in the order of tens of megahertz, proportional to the total number of pixels on the screen) . Many modern microcontrollers generate their clock signal internally and can direct it to a pin if configured properly. If the microcontroller does not have an internal clock generator, said clock signal can still be generated externally and applied to both the clock generation logic (1.4) and the microcontroller (1.2) itself. 10
     a timer module (1.22) with at least one active output by comparison or with PWM mode ("Pulse width modulation"). This peripheral will be used to generate a pulse corresponding to a programmable number of cycles of the square signal of the clock generator (CLKosc). A logical AND type function is performed, through an AND gate (1.41), between this pulse and the clock signal 15 (CLKosc), thereby obtaining a train of a precise number of pulses at the clock input of the display ( PIXCLK). If the DE signal is active each of these pulses will enter the data of a pixel on the screen, while if DE is inactive the pulses correspond to the horizontal or vertical retracement times of the screen. twenty
     one or more Flash memories with serial interface (1.3). The type, number, and capacity of these memories will depend on the color depth of the generated images as well as the total amount of graphic objects that they should store and their respective pixel sizes. For the types of applications envisaged, a color depth of 1, 4 or 25 8 bits per pixel has been considered (although greater color depths could be achieved by connecting more SQI memories in parallel, for example with 3 SQI memories depths of 12 would be achieved bits per pixel):
    or in the case of 1 bit / pixel, a single SPI memory is used;
    or in the case of 4 bits per pixel the memory must be SQI to be able to simultaneously obtain 30 4 bits with the pixel color information; Y,
    or in the case of 8 bits per pixel, two SQI type memories connected in parallel are used.
    All these memories have the characteristic of being able to present a new
    data on the output and increase its address counter automatically for each clock pulse they receive (each positive pulse of the PIXCLK signal), requiring only an initial command from the SPI serial port (1.23) that indicates the operation of reading (active cycle of the MOSI signal) and the initial address of the memory from which the data will be read. Another highlight of this type of memory is that its terminals are always the same, regardless of their capacity, which allows you to choose the device that best suits the needs of the application without redesigning the electronics of the system.
     a clock generation logic (1.4) comprising a switch (1.42) 10 for selecting the input clock signal of the Flash memories (1.3) between the SCK signal from the SPI serial port (1.23) and the corresponding PIXCLK signal to the clock signal of the TFT screen previously generated at the AND gate (1.41). The SCK signal will be selected while the read commands are sent to memory via the SPI serial port (1.23), and then the PIXCLK signal will be selected to send the characters to the screen (1.1) through the corresponding video outputs of flash memories (1.3). In this way, once the Flash memory has been read, the data automatically passes to the screen without the need for direct intervention from the microcontroller CPU. The SCK signal 20 must also be selected when programming the contents of the flash memories from the microcontroller or when reading memory data that is relevant to the microcontroller but not for image generation.
     A logic block related to the generation of color (1.5) This block depends on the desired color depth, having the following 25 implementations:
    o 1 bit color depth per pixel and black background color. Figure 2 shows a particular implementation of this color assignment block (1.5) for this color depth. This is the most basic implementation of the block (1.5) and only requires 4 AND (2.2) doors, so that the pixel will have the color selected by the 4 pins I, R, G, and B of general purpose output GPIO (2.5) when a logical level of 1 is output from the video (SO) output of the SPI flash memory (2.1), or black otherwise. Note that although the images stored in the
    Flash memory are monochrome, its color can be varied depending on its position on the screen, so that we can simultaneously display up to 16 different colors. Depending on the TFT screen chosen, the connection will be (2.3) for a TFT with a resolution of 24 bit / pixel or (2.4) for a TFT with a resolution of 18 bit / pixel. Thus, in a particular embodiment (different connections can be chosen that result in different color palettes) for the generation of images with a color depth of 1 bit per pixel and black background color, the colors obtained can be:
     10
    IRGB COLOR
    --------------------
    0000 Black
    0001 Dark blue
    0010 Dark Green 15
    0011 Dark Cyan
    0100 Dark Red
    0101 Dark Magenta
    0110 Dark Yellow
    0111 Light gray 20
    1000 Dark Gray
    1001 light blue
    1010 light green
    1011 Cyan clear
    1100 Light red 25
    1101 Light Magenta
    1110 Light yellow
    1111 White

    o 1 bit color depth per pixel and selectable background color. Figure 3 shows a particular implementation of this color assignment block (1.5) for this color depth. In this case, a quadruple multiplexer (3.2), 4 pins I, R, G, and B general purpose output GPIO (3.3) are used to assign the color of the foreground characters and another 4 pins I, R, G, and B general purpose output GPIO (3.4) 35 for background color assignment. According to the TFT screen chosen on
    connection will be (3.5) for a TFT with a resolution of 24 bit / pixel or (3.6) for a TFT with a resolution of 18 bit / pixel.
    o Color depth of 4 bits per pixel. Figure 4 shows a particular implementation of this color assignment block (1.5) for this color depth. In this case, the video data comes from an SQI memory (4.1) and is 4 bits, so that it can be connected directly to the video inputs of the TFT screen. Depending on the TFT screen chosen, the connection will be (4.2) for a TFT with a resolution of 24 bit / pixel or (4.3) for a TFT with a resolution of 18 bit / pixel. A resistor (4.4) connected between the MOSI output of the microcontroller and 10 of the SI output of the memory (4.1) is required since when the SQI memory (4.1) is transferred to the 4-bit mode, the SI pin ceases to be input to be output, which would cause a conflict with the MOSI output of the microcontroller. In this implementation each pixel can have up to 16 different colors.
    o 8 bit color depth per pixel. Figure 5 shows a particular implementation of this color allocation block (1.5) for this color depth. In this case, two SQI Flash memories (5.1 and 5.2) are used connected in parallel that provide a total of 8 bits per pixel whose clock signal comes from the clock logic (1.4) described above. The color assignment responds to an RGB332 mode (with 20 3 bits for the red (R0, R1, R2) and green (G0, G1, G2) and 2 bits for the blue component (B0, B1) components. Each pixel can have 256 different colors. The resistors (5.5) connected between the MOSI output of the micro controller and the SI inputs of the memories (4.1) are necessary to mitigate the possible logical conflicts between the output pins SI / D3 of both memories during the data reading phase 4-bit (function D3), as well as with the MOSI pin of the microcontroller. Similarly, the resistances (5.6) between the MISO input and the SO outputs of the memories (4.1) are necessary to mitigate the possible logical conflicts between the output pins SO / D0 of both memories during the reading phase of the data 4 bits (function D0). Depending on the TFT screen chosen, the connection could be (5.3) for a TFT with a resolution of 24 bit / pixel or (5.4) for a TFT with a resolution of 18 bit / pixel.

    Figure 6 shows an example of carrying out a schedule with the control signals that are implemented for the generation of the images on the TFT screens. This exemplary embodiment shows the time schedule corresponding to the single line refresh (6.1) on a TFT screen of the "DE only type, without HSYNC or VSYNC". Said line (6.1) includes the sending of 3 characters (“∞” (6.2), “<” (6.3), and 5 an icon representing a man (6.4)) of the serial flash memories where they are stored on the TFT screen. First, the signal DE (6.5) generated by one of the GPIO output pins (1.24) is activated for the duration of the visible part of the line to enable writing on the TFT screen. Simultaneously the timer module generates the corresponding TIMER signal (6.6) the width of a programmable number 10 of cycles of the clock signal. Thus, once the switch selects the PIXCLK signal (6.7) as the clock input of the serial flash memories, the characters (6.2, 6.3, 6.4) of the line (6.1) are sent, sending one character for each high cycle of the CLKSEL signal (6.8). Each of the high cycles of the PIXCLK signal (6.7) comprises a plurality of pulses, so that in each pulse a pixel of the characters (6.2, 6.3, 6.4) of the line (6.1) that are going to be transmitted is transmitted. show on screen.

    The SPI port clock is used to send read commands to Flash memory, which means sending a total of 32 or 40 clock pulses with the command byte, 3 20 bytes of address and a possible fill byte. PIXCLK (6.7) is used in the subsequent phase of reading data, so that the contents of the Flash memory are transferred to the screen directly, without the intervention of the microcontroller CPU. Therefore, each send of a character (6.2, 6.3, 6.4) from the memories to the screen is preceded by a pulse train of the SCK clock signal (6.9) of the SPI serial port for the 25 character read command to be sent, so the switch will select a signal between PIXCLK (6.7) and SCK (SPI) (6.9) alternately to first send the character read command (RD-cmd) and then send the data (data) of the character to the screen. In this way the composite clock signal, CLK (FLASH) (6.10), is obtained at the clock input of the Flash memories. 30

    Additionally, the system sends, between every two lines, a certain number of clock pulses (6.13), depending on the display model, which signal the beginning of a new line. A larger number of pulses with the low DE signal would signal the
    Start of the image frame or vertical retracement (not shown in Fig. 6).

    The total number of clock pulses generated in the PIXCLK signal (6.7) is controlled by the TIMER timer output (6.6), while CLKSEL (6.8) indicates whether the SCK clock signal of the SPI port (6.9) reaches the Flash memory. ) or the PIXCLK 5 signal (6.7). It should also be noted that the PIXCLK (6.7) and SCK (SPI) (6.9) signals can be generated simultaneously if the CLKSEL (6.8) signal is inactive, which can be useful for reducing PIXCLK downtimes and thus increasing the frequency of screen refresh. In particular, this possibility can be taken advantage of in the delayed times or if in the image we have large gaps 10 (6.14) between the characters (6.2, 6.3, 6.4).

    Flash memories have an additional input, / CS (6.11), which must be at a low level during the execution of the character read commands (RD-cmd) the data send commands (data) of the CLK signal (6.10 ) and in which a lowering edge indicates the first bit of the aforementioned commands. In Fig. 6 the temporal evolution of this signal is shown, which is only set to a high level briefly before sending a new read command to the Flash memories.

    The VIDEO signal (6.12) is obtained at the outputs of the Flash memories, and in the example of Fig. 6 it is a single bit, which will generate monochrome images (blocks of color generation as shown in Fig. 2 or Fig. 3). The VIDEO signal (6.12) can have an arbitrary value during the reading of the characters, according to the data programmed in the flash memories, although in Fig. 6 the trace corresponding to the video line is shown superimposed (6.1) particular of this example.
    权利要求:
    Claims (15)
    [1]

    1. Image generation system on TFT screens, characterized in that it comprises a TFT screen, at least one flash memory with serial interface where characters to be displayed on the TFT screen and a microcontroller are stored, 5 where the microcontroller comprises:
     - a timer module configured to generate a signal proportional to a programmable number of cycles of a clock signal;
     -a serial peripheral interface port configured to manage the at least one flash memory; 10
     - general purpose input / output pins configured to enable writing on the TFT screen;
     wherein the system additionally comprises means for generating a clock input signal of the TFT screen from the signal generated by the timer module and the clock signal and a switch that selects a clock signal 15 of the at least a flash memory between the clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, so that the characters in the at least one flash memory are transmitted directly to the TFT screen.
     twenty
    [2]
    2. Image generation system on TFT screens, according to claim 1, comprising an internal clock for the generation of the clock signal.

    [3]
    3. Image generation system on TFT screens, according to claim 1, wherein the timer module comprises an active output selected from an output by comparison and an output with pulse width modulation.

    [4]
    4. Image generation system on TFT screens, according to claim 1, wherein the at least one flash memory with serial interface is a serial peripheral interface memory. 30

    [5]
    5. Image generation system on TFT screens, according to claim 1, wherein the at least one flash memory with serial interface is a quad-serial serial input / output memory.
    [6]
    6. Image generation system on TFT screens, according to claim 1, wherein the at least one flash memory with serial interface are two quad serial serial input / output memories connected in parallel.

    [7]
    7. Image generation system on TFT screens, according to any one of the 5 preceding claims, comprising a color allocation module connected to the at least one flash memory to assign colors to the characters shown on the TFT screen.

    [8]
    8. Image generation system on TFT screens, according to claims 4 10 and 7, wherein the color allocation module comprises 4 AND doors, each AND door having a first common input connected to a video output of the memory of serial peripheral interface and a second input, where the second input of each AND gate is connected, respectively, to one of the general purpose input / output pins, so that the color assignment module 15 is configured to generate characters Monochrome with black background.

    [9]
    9. Image generation system on TFT screens, according to claims 4 and 7, wherein the color allocation module comprises a quadruplex multiplexer with an input connected to a video output of the peripheral interface memory in series 20, 4 first inputs connected respectively to 4 general purpose input / output pins to assign a color to each character and 4 second inputs respectively connected to 4 general purpose input / output pins to assign a color to a background, so that the module Color mapping is set to generate monochrome characters with monochrome background. 25

    [10]
    10. Image generation system on TFT screens, according to claim 5, wherein the quad serial input / output memory has 4 image outputs directly connected to image inputs of the TFT screen, the system being configured to generate characters with color depths of 4 bits per 30 pixel.

    [11]
    11. Image generation system on TFT screens, according to claim 6, wherein each quadruple serial input / output memory has 4 image outputs
    connected directly to some image inputs of the TFT screen, the system being configured in an RGB 332 mode to generate characters with color depths of 8 bits per pixel.

    [12]
    12. Method of generating images on TFT screens using the system described in any one of the preceding claims, characterized in that it comprises the steps of:
     - generate in the timer module a signal proportional to a programmable number of cycles of the clock signal;
     - activate a write mode of the TFT display by means of one of the 10 general-purpose output pins of the microcontroller for a duration of a visible part of a character line;
     - generate a clock input signal from the TFT screen from the signal generated by the timer module and the clock signal;
     -select by means of a switch a signal between the input signal of the clock of the TFT screen and a clock signal of the serial peripheral interface port, where the selected signal is the clock input signal of the at least one flash memory ; Y,
     - send from the at least one flash memory a character of the character line directly to the TFT screen when the switch selects the clock input signal 20 of the TFT screen and the clock input signal of the TFT screen is active.

    [13]
    13. Procedure for generating images on TFT screens, according to claim 12, wherein it comprises assigning color to the characters shown in the TFT screen.

    [14]
    14. Method of generating images on TFT screens, according to claim 12, comprising sending a number of clock pulses between two active cycles of the clock input signal of the TFT screen to mark a start of a new line. of characters.

    [15]
    15.- Image generation procedure on TFT screens, according to claim 12, that when the switch selects the clock signal from the port of
    Serial peripheral interface, the procedure comprises sending read commands to the at least one flash memory.
    类似技术:
    公开号 | 公开日 | 专利标题
    JP4360930B2|2009-11-11|Image display device
    ES2823736T3|2021-05-10|Procedures for exciting electro-optical display devices
    TWI439992B|2014-06-01|Controlling display updates for electro-optic displays
    KR20090031343A|2009-03-25|Video display driver with gamma control
    KR20070006744A|2007-01-11|Electrophoretic display panel
    TW200907987A|2009-02-16|Gamma voltage setting IC
    TW200403610A|2004-03-01|An electrophoretic display
    US9501996B2|2016-11-22|Control method
    US20180151155A1|2018-05-31|Driving system supporting multiple display modes
    KR101420472B1|2014-07-16|Organic light emitting diode display device and drving method thereof
    US20170116946A1|2017-04-27|Display device and display method
    CN108717838B|2021-05-25|Silicon-based micro display and driving circuit thereof
    CN103310747A|2013-09-18|Liquid crystal display device, driving method of liquid crystal display device and electronic apparatus
    US20130222441A1|2013-08-29|Display device, and driving circuit and method thereof
    ES2606299B1|2018-01-09|SYSTEM AND PROCEDURE FOR GENERATING IMAGES ON TFT SCREENS
    GB2507610A|2014-05-07|Display device including a voltage monitor unit and method for driving the display device.
    US10685612B2|2020-06-16|Liquid crystal display device and liquid crystal display method
    JP2009042446A|2009-02-26|Display device
    JP6877890B2|2021-05-26|Display panel drive device, display panel drive method using the display panel drive device, and display device including the display panel drive device.
    US20150170594A1|2015-06-18|Data driver and display device using the same
    US10210829B2|2019-02-19|Display apparatus and method of operation
    JP2010127829A|2010-06-10|Integrated circuit device and electronic device
    TWI626636B|2018-06-11|Processor for setting frame rate and method of setting frame rate
    CN110751924A|2020-02-04|Micro-LED display screen controlled in split screen mode
    US20170076644A1|2017-03-16|Display device, method of driving the same, and image display system
    同族专利:
    公开号 | 公开日
    ES2606299B1|2018-01-09|
    WO2017032911A1|2017-03-02|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20070188313A1|2006-02-13|2007-08-16|Promate Electronic Co., Ltd.|Multi-purposed in-vehicle information display module|
    US8284179B2|2008-02-21|2012-10-09|Himax Technologies Limited|Timing controller for reducing power consumption and display device having the same|
    US9250695B2|2013-03-15|2016-02-02|Google Technology Holdings LLC|Method and apparatus for displaying a predetermined image on a display panel of an electronic device when the electronic device is operating in a reduced power mode of operation|CN112269338A|2020-10-23|2021-01-26|阳光电源股份有限公司|GPIO-based digital controller communication method and system|
    法律状态:
    2018-01-09| FG2A| Definitive protection|Ref document number: 2606299 Country of ref document: ES Kind code of ref document: B1 Effective date: 20180109 |
    优先权:
    申请号 | 申请日 | 专利标题
    ES201531213A|ES2606299B1|2015-08-21|2015-08-21|SYSTEM AND PROCEDURE FOR GENERATING IMAGES ON TFT SCREENS|ES201531213A| ES2606299B1|2015-08-21|2015-08-21|SYSTEM AND PROCEDURE FOR GENERATING IMAGES ON TFT SCREENS|
    PCT/ES2016/070511| WO2017032911A1|2015-08-21|2016-07-07|System and method for generating images on tft screens|
    [返回顶部]